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» A FPGA Based Forth Microprocessor
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CODES
2007
IEEE
14 years 1 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid
FCCM
2006
IEEE
113views VLSI» more  FCCM 2006»
14 years 1 months ago
GraphStep: A System Architecture for Sparse-Graph Algorithms
— Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The gr...
Michael DeLorimier, Nachiket Kapre, Nikil Mehta, D...
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
14 years 1 months ago
A Field Programmable RFID Tag and Associated Design Flow
Current Radio Frequency Identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable,...
Alex K. Jones, Raymond R. Hoare, Swapna R. Donthar...
CODES
2005
IEEE
13 years 9 months ago
Hardware/software partitioning of software binaries: a case study of H.264 decode
We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application’s binary are competitive with parti...
Greg Stitt, Frank Vahid, Gordon McGregor, Brian Ei...