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FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 1 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
MOBIHOC
2009
ACM
14 years 8 months ago
WARPnet: clean slate research on deployed wireless networks
In this demo we present the Wireless Open-Access Research Platform for Networks (WARPnet), a research testbed aimed at performing experiments at the network level. The platform is...
Siddharth Gupta, Chris Hunter, Patrick Murphy, Ash...
ISCAS
2007
IEEE
176views Hardware» more  ISCAS 2007»
14 years 1 months ago
SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier
— Simple Power Analysis (SPA) was applied to an RSA processor with a high-radix Montgomery multiplier on an FPGA platform, and the different characteristics of power waveforms ca...
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Ak...
RSP
2005
IEEE
14 years 1 months ago
Prototyping a Residential Gateway Using Xilinx ISE
This paper presents a residential gateway (RG) prototyping process using Xilinx Integrated Software Environment (ISE) version 6.1i. The RG was designed for broadband residential m...
S. W. Song, J. D. Zheng, William B. Gardner
IPPS
1998
IEEE
13 years 11 months ago
A Java Development and Runtime Environment for Reconfigurable Computing
Fast runtime reconfigurable hardware enables system designers to swap hardware into and out of an FPGA much as the pages of virtual memory are swapped into and out of virtual memor...
Don Davis, Michael Barr, Toby Bennett, Stephen Edw...