68 search results - page 6 / 14 » A Family of Logical Fault Models for Reversible Circuits |
COCO
2008
Springer
13 years 9 months ago
2008
Springer
We introduce a simple game family, called Constraint Logic, where players reverse edges in a directed graph while satisfying vertex in-flow constraints. This game family can be in...
ITC
2003
IEEE
14 years 22 days ago
2003
IEEE
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...
ET
2010
13 years 6 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
CSREAESA
2003
13 years 8 months ago
2003
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...