36 search results - page 3 / 8 » A Fast Two-level Logic Minimizer |
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper, we prese...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
? An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for co...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
ASAP
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...