103 search results - page 4 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
ET
1998
13 years 7 months ago
1998
This paper explores the design of efficient test sets and test-pattern generators for online BIST. The target applications are high-performance, scalable datapath circuits for whi...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
VTS
2002
IEEE
14 years 20 days ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vector...