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» A Field-Programmable Mixed-Analog-Digital Array
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EH
2003
IEEE
138views Hardware» more  EH 2003»
14 years 21 days ago
Implementing Evolution of FIR-Filters Efficiently in an FPGA
Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for Evolvable hardware (EHW) ...
Knut Arne Vinger, Jim Torresen
FPL
2000
Springer
95views Hardware» more  FPL 2000»
13 years 11 months ago
It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures
Following the simple Programmable Logic Device (SPLD) and Field Programmable Gate Array (FPGA) generations a third generation of programmable logic technologies is now reaching the...
Tom Kean
FPL
2008
Springer
117views Hardware» more  FPL 2008»
13 years 9 months ago
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter
This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detec...
Roberto Perez-Andrade, René Cumplido, Claud...
CSREAESA
2006
13 years 8 months ago
In-House Built Bipedal Walking Robot
In this project, an in-house built bipedal walking Robot uses two direct current gear motors to power its legs. Each leg could bend at the knee to assist the walking routines. In ...
Kok-Swee Sim, Yee Kin Lum, Chih Ping Tso
ESANN
2006
13 years 8 months ago
Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choic...
Benjamin Schrauwen, Jan M. Van Campenhout