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VTC
2008
IEEE
14 years 1 months ago
Construction of Regular Quasi-Cyclic Protograph LDPC codes based on Vandermonde Matrices
Abstract— In this contribution, we investigate the attainable performance of quasi-cyclic (QC) protograph Low-Density Parity-Check (LDPC) codes for transmission over both Additiv...
Nicholas Bonello, Sheng Chen, Lajos Hanzo
DATE
2005
IEEE
176views Hardware» more  DATE 2005»
14 years 1 months ago
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates wi...
Frank Kienle, Torben Brack, Norbert Wehn
FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
14 years 23 days ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
MSS
2007
IEEE
82views Hardware» more  MSS 2007»
14 years 1 months ago
Tornado Codes for MAID Archival Storage
This paper examines the application of Tornado Codes, a class of low density parity check (LDPC) erasure codes, to archival storage systems based on massive arrays of idle disks (...
Matthew Woitaszek, Henry M. Tufo
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 9 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy