State minimization of incompletely specifiedmachinesis an important step of FSM synthesis. An exact algorithm consists of generation of prime compatibles and solution of a binate ...
Timothy Kam, Tiziano Villa, Robert K. Brayton, Alb...
Ordered Binary Decision Diagrams (BDDs) are frequently used in logic synthesis. In this paper a new exact BDD minimization algorithm is presented, which is based on state space se...
None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and auto...
We present a novel method for state minimization of incompletely-specified finite state machines. Where classic methods simply minimize the number of states, ours directly addre...
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...