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» A Functional DBPL Revealing High Level Optimizations
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ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
14 years 1 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
LCTRTS
2007
Springer
14 years 1 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
COMGEO
1999
ACM
13 years 7 months ago
Multiresolution hierarchies on unstructured triangle meshes
The use of polygonal meshes for the representation of highly complex geometric objects has become the de facto standard in most computer graphics applications. Especially triangle...
Leif Kobbelt, Jens Vorsatz, Hans-Peter Seidel
PE
2008
Springer
173views Optimization» more  PE 2008»
13 years 7 months ago
Improving fairness in a WRED-based DiffServ network: A fluid-flow approach
The DiffServ architecture has been proposed as a scalable approach for upgrading the Internet, adding service differentiation functionalities. However, several aspects of this arc...
Mario Barbera, Alfio Lombardo, Giovanni Schembra, ...
VISUALIZATION
2005
IEEE
14 years 1 months ago
A Shader-Based Parallel Rendering Framework
Existing parallel or remote rendering solutions rely on communicating pixels, OpenGL commands, scene-graph changes or application-specific data. We propose an intermediate soluti...
Jérémie Allard, Bruno Raffin