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DAC
2009
ACM
14 years 2 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A robust detailed placement for mixed-size IC designs
— The rapid increase in IC design complexity and wide-spread use of intellectual-property (IP) blocks have made the so-called mixed-size placement a very important topic in recen...
Jason Cong, Min Xie
CASES
2004
ACM
14 years 26 days ago
Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations
Many optimization techniques, including several targeted specifically at embedded systems, depend on the ability to calculate the number of elements that satisfy certain conditio...
Sven Verdoolaege, Rachid Seghir, Kristof Beyls, Vi...
SIGMETRICS
2008
ACM
116views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
Optimal sampling in state space models with applications to network monitoring
Advances in networking technology have enabled network engineers to use sampled data from routers to estimate network flow volumes and track them over time. However, low sampling ...
Harsh Singhal, George Michailidis
TCAD
2010
88views more  TCAD 2010»
13 years 2 months ago
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan