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» A Graph Reduction Approach to Symbolic Circuit Analysis
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DAC
1998
ACM
14 years 8 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
AHS
2006
IEEE
164views Hardware» more  AHS 2006»
14 years 1 months ago
Automatic Hybrid Genetic Algorithm Based Printed Circuit Board Inspection
The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a Genetic Algorithm (GA) based framework in order to provide an ad...
Syamsiah Mashohor, Jonathan R. Evans, Ahmet T. Erd...
SCP
1998
134views more  SCP 1998»
13 years 7 months ago
Abstract Interpretation Using Typed Decision Graphs
Interpretation Using Typed Decision Graphs Laurent Mauborgne LIENS, ´Ecole Normale Sup´erieure, 45 rue d’Ulm, 75230 Paris cedex 05, France Abstract. This article presents a way...
Laurent Mauborgne
DAM
2007
79views more  DAM 2007»
13 years 7 months ago
Necessary conditions for multistationarity in discrete dynamical systems
R. Thomas conjectured, twenty years ago, that the presence of a positive circuit in the interaction graph of a dynamical system is a necessary condition for the presence of severa...
Adrien Richard, Jean-Paul Comet
ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
13 years 5 months ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng