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VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
14 years 8 months ago
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
| This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some ac...
Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, D...
DATE
2008
IEEE
170views Hardware» more  DATE 2008»
14 years 2 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
CAV
2004
Springer
99views Hardware» more  CAV 2004»
14 years 28 days ago
Range Allocation for Separation Logic
Abstract. Separation Logic consists of a Boolean combination of predicates of the form vi ≥ vj +c where c is a constant and vi, vj are variables of some ordered infinite type li...
Muralidhar Talupur, Nishant Sinha, Ofer Strichman,...
HYBRID
2007
Springer
13 years 11 months ago
Qualitative Analysis of Nonlinear Biochemical Networks with Piecewise-Affine Functions
Abstract. Nonlinearities and the lack of accurate quantitative information considerably hamper modeling and system analysis of biochemical networks. Here we propose a procedure for...
M. W. J. M. Musters, Hidde de Jong, P. P. J. van d...
FMCAD
2009
Springer
14 years 2 months ago
Software model checking via large-block encoding
Abstract—Several successful approaches to software verificabased on the construction and analysis of an abstract reachability tree (ART). The ART represents unwindings of the co...
Dirk Beyer, Alessandro Cimatti, Alberto Griggio, M...