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» A Graph Reduction Approach to Symbolic Circuit Analysis
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ICDAR
2009
IEEE
14 years 2 months ago
Graphic Symbol Recognition Using Graph Based Signature and Bayesian Network Classifier
We present a new approach for recognition of complex graphic symbols in technical documents. Graphic symbol recognition is a well known challenge in the field of document image an...
Muhammad Muzzamil Luqman, Thierry Brouard, Jean-Yv...
ISLPED
1997
ACM
83views Hardware» more  ISLPED 1997»
13 years 11 months ago
A symbolic algorithm for low-power sequential synthesis
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...
Balakrishna Kumthekar, In-Ho Moon, Fabio Somenzi
DATE
2004
IEEE
157views Hardware» more  DATE 2004»
13 years 11 months ago
Hierarchical Modeling and Simulation of Large Analog Circuits
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...
Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
DAC
2006
ACM
14 years 8 months ago
MARS-C: modeling and reduction of soft errors in combinational circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
Natasa Miskov-Zivanov, Diana Marculescu
ICDAR
2003
IEEE
14 years 24 days ago
An Evolutionary Algorithm for General Symbol Segmentation
A new system is presented for general symbol segmentation, which is applicable for segmentation of any connected string of symbols, including characters and line diagrams. Using a...
Stephen Pearce, Maher Ahmed