136 search results - page 4 / 28 » A Graph Reduction Approach to Symbolic Circuit Analysis |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Reversible quantum logic plays an important role in quantum computing. In this paper, we propose an approach to optimally synthesize quantum circuits by symbolic reachability anal...
PLDI
2009
ACM
14 years 2 months ago
2009
ACM
Symbolic analysis shows promise as a foundation for bug-finding, specification inference, verification, and test generation. This paper addresses demand-driven symbolic analysi...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...