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SIGMETRICS
2005
ACM
110views Hardware» more  SIGMETRICS 2005»
14 years 2 months ago
Empirical evaluation of multi-level buffer cache collaboration for storage systems
To bridge the increasing processor-disk performance gap, buffer caches are used in both storage clients (e.g. database systems) and storage servers to reduce the number of slow di...
Zhifeng Chen, Yan Zhang, Yuanyuan Zhou, Heidi Scot...
MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
14 years 2 months ago
Three extensions to register integration
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
Vlad Petric, Anne Bracy, Amir Roth
MST
2010
146views more  MST 2010»
13 years 4 months ago
The Cache-Oblivious Gaussian Elimination Paradigm: Theoretical Framework, Parallelization and Experimental Evaluation
We consider triply-nested loops of the type that occur in the standard Gaussian elimination algorithm, which we denote by GEP (or the Gaussian Elimination Paradigm). We present tw...
Rezaul Alam Chowdhury, Vijaya Ramachandran
FP
1989
124views Formal Methods» more  FP 1989»
14 years 1 months ago
Deriving the Fast Fourier Algorithm by Calculation
This paper reports an explanation of an intricate algorithm in the terms of a potentially mechanisable rigorous-development method. It uses notations and techniques of Sheeran 1] ...
Geraint Jones
DATE
2010
IEEE
118views Hardware» more  DATE 2010»
13 years 7 months ago
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
Minje Jun, Sungroh Yoon, Eui-Young Chung