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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
16 years 1 days ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
16 years 22 days ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
DAMON
2009
Springer
16 years 20 days ago
Cache-conscious buffering for database operators with state
Database processes must be cache-efficient to effectively utilize modern hardware. In this paper, we analyze the importance of temporal locality and the resultant cache behavior ...
John Cieslewicz, William Mee, Kenneth A. Ross
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 15 days ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
MICRO
2007
IEEE
128views Hardware» more  MICRO 2007»
16 years 11 days ago
A Framework for Providing Quality of Service in Chip Multi-Processors
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer