In this paper we propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified b...
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
The use of multilayer perceptrons (MLP) with threshold functions (binary step function activations) greatly reduces the complexity of the hardware implementation of neural networks...
Vassilis P. Plagianakos, George D. Magoulas, Micha...
This work presents a soft IP description of Rijndael, the Advanced Encryption Standard (AES) of National Institute of Standards and Technology (NIST). This Rijndael implementation...
Alex Panato, Marcelo Barcelos, Ricardo Augusto da ...