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ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
14 years 6 months ago
Evaluating Techniques for Exploiting Instruction Slack
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efï¬...
Yau Chin, John Sheu, David Brooks
ISCAS
1999
IEEE
116views Hardware» more  ISCAS 1999»
14 years 1 months ago
A coefficient segmentation algorithm for low power implementation of FIR filters
The authors present a multiplication algorithm for low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual...
Ahmet T. Erdogan, Tughrul Arslan
SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
14 years 3 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
COMSWARE
2008
IEEE
14 years 3 months ago
On implementing security at the transport layer
— We design a framework that implements security at the TCP layer to meet the necessity for a practical and truly end-to-end security solution. We call our framework TCPsec. TCPs...
Swaminathan Pichumani, Sneha Kumar Kasera
AUSDM
2008
Springer
238views Data Mining» more  AUSDM 2008»
13 years 11 months ago
Graphics Hardware based Efficient and Scalable Fuzzy C-Means Clustering
The exceptional growth of graphics hardware in programmability and data processing speed in the past few years has fuelled extensive research in using it for general purpose compu...
S. A. Arul Shalom, Manoranjan Dash, Minh Tue