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MICRO
2003
IEEE
100views Hardware» more  MICRO 2003»
14 years 2 months ago
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System
Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we imp...
Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobb...
ISCA
1989
IEEE
109views Hardware» more  ISCA 1989»
14 years 1 months ago
Improving Performance of Small On-Chip Instruction Caches
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
Matthew K. Farrens, Andrew R. Pleszkun
VLSID
2006
IEEE
119views VLSI» more  VLSID 2006»
14 years 9 months ago
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
GLOBECOM
2009
IEEE
14 years 3 months ago
Lightweight Jammer Localization in Wireless Networks: System Design and Implementation
—Jamming attacks have become prevalent during the last few years, due to the shared nature and the open access to the wireless medium. Finding the location of a jamming device is...
Konstantinos Pelechrinis, Iordanis Koutsopoulos, I...
ICNP
2007
IEEE
14 years 3 months ago
Design and Implementation of Cross-Domain Cooperative Firewall
Security and privacy are two major concerns in supporting roaming users across administrative domains. In current practices, a roaming user often uses encrypted tunnels, e.g., Virt...
Jerry Cheng, Hao Yang, Starsky H. Y. Wong, Petros ...