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» A High Level Power Model for the Nostrum NoC
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DATE
1998
IEEE
75views Hardware» more  DATE 1998»
13 years 11 months ago
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs
Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at...
Dirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebe...
MVA
2007
175views Computer Vision» more  MVA 2007»
13 years 9 months ago
Noisy Image Segmentation Based on a Level Set Evolution
In this paper, we propose a new hybrid model for active contour image segmentation, which is able to segment non-uniform noisy images efficiently. The model is a combination betwe...
Khaled Issa, Hiroshi Nagahashi
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
13 years 12 months ago
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
Markus Bühler, Matthias Papesch, K. Kapp, Utz...
ICDM
2003
IEEE
111views Data Mining» more  ICDM 2003»
14 years 25 days ago
OP-Cluster: Clustering by Tendency in High Dimensional Space
Clustering is the process of grouping a set of objects into classes of similar objects. Because of unknownness of the hidden patterns in the data sets, the definition of similari...
Jinze Liu, Wei Wang 0010
APCCAS
2006
IEEE
304views Hardware» more  APCCAS 2006»
14 years 1 months ago
Low-Power Bus Transform Coding for Multilevel Signals
Abstract— In this paper, we propose a novel extension of BusInvert coding to handle 4-level pulse amplitude modulated (PAM-4) signals. A generalized mathematical model for energy...
Fakhrul Zaman Rokhani, Gerald E. Sobelman