Sciweavers

3104 search results - page 117 / 621
» A High Performance Kernel-Less Operating System Architecture
Sort
View
DATE
2003
IEEE
131views Hardware» more  DATE 2003»
14 years 1 months ago
High Speed and Highly Testable Parallel Two-Rail Code Checker
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
Martin Omaña, Daniele Rossi, Cecilia Metra
IADIS
2004
13 years 9 months ago
High School Students and the Digital Age
The computer revolution and Internet expansion in parallel with multimedia advancement have radically changed the way that knowledge is disseminated. All over the world researches...
Paraskevi Mentzelou, Tanya Kyriakidou, Veronica Sa...
COMCOM
2004
98views more  COMCOM 2004»
13 years 7 months ago
End system multicast: an architectural infrastructure and topological optimization
Although IP-multicast has been proposed and investigated for years, there are major problems inherent in the IP-multicasting technique, e.g., difficulty to scale up the system, di...
Starsky H. Y. Wong, John C. S. Lui
TPDS
2002
105views more  TPDS 2002»
13 years 7 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
TVLSI
2010
13 years 2 months ago
Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-
Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are ...
Hai Lin, Yunsi Fei, Xuan Guan, Zhijie Jerry Shi