122 search results - page 11 / 25 » A High-Performance Hardware Architecture for Spectral Hash A... |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, ...
GECCO
2007
Springer
14 years 1 months ago
2007
Springer
In recent years the computing power of graphics cards has increased significantly. Indeed, the growth in the computing power of these graphics cards is now several orders of magn...
ARITH
2007
IEEE
14 years 1 months ago
2007
IEEE
We describe a new method to perform the modular exponentiation operation, i.e., the computation of c = me mod n, where c, m, e and n are large integers. The new method uses the di...
DATE
2010
IEEE
14 years 17 days ago
2010
IEEE
—Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low comput...
ASAP
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...