Sciweavers

354 search results - page 44 / 71
» A Hybrid Tool for the Performance Evaluation of NUMA Archite...
Sort
View
CODES
2006
IEEE
14 years 1 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
HPCS
2006
IEEE
14 years 1 months ago
Toward a Software Infrastructure for the Cyclops-64 Cellular Architecture
This paper presents the initial design of the Cyclops-64 (C64) system software infrastructure and tools under development as a joint effort between IBM T.J. Watson Research Center...
Juan del Cuvillo, Weirong Zhu, Ziang Hu, Guang R. ...
ASAP
2008
IEEE
82views Hardware» more  ASAP 2008»
14 years 2 months ago
Run-time thread sorting to expose data-level parallelism
We address the problem of data parallel processing for computational quantum chemistry (CQC). CQC is a computationally demanding tool to study the electronic structure of molecule...
Tirath Ramdas, Gregory K. Egan, David Abramson, Ki...
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
14 years 4 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
MSWIM
2004
ACM
14 years 29 days ago
An enhanced HCF for IEEE 802.11e wireless networks
In this paper the behavior of the upcoming MAC protocol for wireless LANs IEEE 802.11e is investigated. Based on the results, we propose an enhancement for Hybrid Coordination Fun...
Balasubramanian Appiah Venkatakrishnan, S. Selvake...