A hierarchical modeling framework for on-chip communication architectures

— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication architecture should be included in any quantitative evaluation of system design during design space exploration. While there are several mature methodologies for the modeling and evaluation of architectures of processing elements, there is relatively little work done in modeling of an extensive range of on-chip communication architectures, and integrating this into a single modeling and simulation environment combining processing element and on-chip communication architectures. This paper describes a modeling framework with accompanying simulation tools that attempts to fill this gap. Based on an analysis of a wide range of on-chip communication architectures, we describe how a specific hierarchical class library can be used to develop new on-chip communication architectures, or variants of existing ones with rela...

• Type: Conference
• Year: 2002
• Where: ICCAD
• Authors: Xinping Zhu, Sharad Malik
• Keywords: Hardware, ICCAD 2002, On-chip Bus Systems, On-chip Communication Architectures, On-chip Packet