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» A Java processor architecture for embedded real-time systems
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LCPC
2005
Springer
14 years 1 months ago
Manipulating MAXLIVE for Spill-Free Register Allocation
Abstract. Many embedded systems use single-chip microcontrollers which have no on-chip RAM. In such a system, the processor registers must hold all live data values. Nanocontroller...
Shashi Deepa Arcot, Henry G. Dietz, Sarojini Priya...
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 8 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
DAC
2004
ACM
14 years 8 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
IFIP
1998
Springer
13 years 11 months ago
Combining Static Partitioning with Dynamic Distribution of Threads
This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel an...
Ronald Moore, Melanie Klang, Bernd Klauer, Klaus W...
ASAP
2007
IEEE
153views Hardware» more  ASAP 2007»
13 years 7 months ago
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
Haibo Zhu, Partha Pratim Pande, Cristian Grecu