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» A Java processor architecture for embedded real-time systems
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109
Voted
ISLPED
1999
ACM
100views Hardware» more  ISLPED 1999»
15 years 7 months ago
Selective instruction compression for memory energy reduction in embedded systems
We propose a technique for reducing the energy required by rmware code to execute on embedded systems. The method is based on the idea of compressing the most commonly executed in...
Luca Benini, Alberto Macii, Enrico Macii, Massimo ...
118
Voted
ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
15 years 7 months ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf
104
Voted
ARCS
2004
Springer
15 years 8 months ago
Cryptonite - A Programmable Crypto Processor Architecture for High-Bandwidth Applications
Cryptographic methods are widely used within networking and digital rights management. Numerous algorithms exist, e.g. spanning VPNs or distributing sensitive data over a shared ne...
Rainer Buchty, Nevin Heintze, Dino Oliva
139
Voted
LCTRTS
2007
Springer
15 years 8 months ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
123
Voted
RTAS
2008
IEEE
15 years 9 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang