We introduce a refinement strategy to bring the parallel performance analysis closer to the user. The analysis starts with a simple high-level performance model. It is based on fir...
Jan Lemeire, Andy Crijns, John Crijns, Erik F. Dir...
Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and...
While existing mathematical descriptions can accurately account for phenomena at microscopic scales (e.g. molecular dynamics), these are often high-dimensional, stochastic and thei...
Wireplanning is an approach in which the timing of inputoutput paths is planned before modules are specified, synthesized or sized. If these global wires are optimally segmented ...
Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. ...
Working in collaboration with Spain-based retailer Zara, we address the problem of distributing over time a limited amount of inventory across all the stores in a fast-fashion ret...