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FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
15 years 10 months ago
Mixing buffers and pass transistors in FPGA routing architectures
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
Mike Sheng, Jonathan Rose
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
15 years 10 months ago
Optimal latch mapping and retiming within a tree
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
Joel Grodstein, Eric Lehman, Heather Harkness, Her...
C5
2004
IEEE
15 years 9 months ago
Skeleton - Easy Simulation System
Skeleton is a visual scripting environment as an extension of Squeak etoy [1] with Connectors [2] system to make mathematical and physical simulation for non professional computer...
Takashi Yamamiya
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
ECOWS
2008
Springer
15 years 7 months ago
Beyond Soundness: On the Semantic Consistency of Executable Process Models
Executable business process models build on the specification of process activities, their implemented business functions (e.g., Web services) and the control flow between these a...
Ingo Weber, Jörg Hoffmann, Jan Mendling