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» A Logic for Virtual Memory
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DAC
1999
ACM
15 years 9 months ago
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. ...
ESOP
2010
Springer
16 years 2 months ago
Separating Shape Graphs
Detailed memory models that expose individual fields are necessary to precisely analyze code that makes use of low-level aspects such as, pointers to fields and untagged unions. Ye...
Vincent Laviron, Bor-Yuh Evan Chang and Xavier Riv...
APLAS
2009
ACM
15 years 11 months ago
Proving Copyless Message Passing
Handling concurrency using a shared memory and locks is tedious and error-prone. One solution is to use message passing instead. We study here a particular, contract-based flavor ...
Jules Villard, Étienne Lozes, Cristiano Cal...
IPPS
2002
IEEE
15 years 9 months ago
Compile/Run-Time Support for Thread Migration
This paper describes a generic mechanism to migrate threads in heterogeneous distributed environments. To maintain high portability and flexibility, thread migration is implement...
Hai Jiang, Vipin Chaudhary
FPL
2006
Springer
219views Hardware» more  FPL 2006»
15 years 8 months ago
FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks
This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously in...
François-Xavier Standaert, Gaël Rouvro...