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» A Logic for Virtual Memory
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EH
1999
IEEE
161views Hardware» more  EH 1999»
15 years 9 months ago
Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS
-- This paper describes the operation of a field programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (...
John F. McDonald, Bryan S. Goda
DAC
1999
ACM
16 years 5 months ago
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...
Jason Cong, Honching Li, Chang Wu
ICCD
2005
IEEE
135views Hardware» more  ICCD 2005»
16 years 1 months ago
Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults
In this paper, we make two major contributions: First, to enhance Boolean learning, we propose a new class of logic implications called extended forward implications. Using a nove...
Manan Syal, Rajat Arora, Michael S. Hsiao
DATE
2008
IEEE
115views Hardware» more  DATE 2008»
15 years 11 months ago
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
LICS
2005
IEEE
15 years 10 months ago
Certifying Compilation for a Language with Stack Allocation
This paper describes an assembly-language type system capable of ensuring memory safety in the presence of both heap and stack allocation. The type system uses linear logic and a ...
Limin Jia, Frances Spalding, David Walker, Neal Gl...