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RTSS
1997
IEEE
15 years 9 months ago
On-the-fly symbolic model checking for real-time systems
This paper presents an on-the-fly and symbolic algorithm for checking whether a timed automaton satisfies a formula of a timed temporal logic which is more expressive than TCTL....
Ahmed Bouajjani, Stavros Tripakis, Sergio Yovine
ICCAD
1996
IEEE
119views Hardware» more  ICCAD 1996»
15 years 8 months ago
An algorithm for synthesis of system-level interface circuits
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...
Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
PARLE
1992
15 years 8 months ago
Reliable Communication in VPL
We compare di erent degrees of architecture abstraction and communication reliability in distributed programming languages. A nearly architecture independent logic programming lang...
eva Kühn, Franz Puntigam
FPGA
2006
ACM
93views FPGA» more  FPGA 2006»
15 years 8 months ago
Measuring the gap between FPGAs and ASICs
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power cons...
Ian Kuon, Jonathan Rose
ERSA
2009
109views Hardware» more  ERSA 2009»
15 years 2 months ago
An Implementation of Security Extensions for Data Integrity and Confidentiality in Soft-Core Processors
An increasing number of embedded system solutions in space, military, and consumer electronics applications rely on processor cores inside reconfigurable logic devices. Ensuring da...
Austin Rogers, Aleksandar Milenkovic