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DAC
2006
ACM
16 years 5 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
DAC
2006
ACM
16 years 5 months ago
Efficient SAT-based Boolean matching for FPGA technology mapping
Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
Sean Safarpour, Andreas G. Veneris, Gregg Baeckler...
WWW
2007
ACM
16 years 5 months ago
A unified platform for data driven web applications with automatic client-server partitioning
Data-driven web applications are usually structured in three tiers with different programming models at each tier. This division forces developers to manually partition applicatio...
Fan Yang 0002, Nitin Gupta 0003, Nicholas Gerner, ...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 4 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
HPCA
2001
IEEE
16 years 4 months ago
An Architectural Evaluation of Java TPC-W
The use of the Java programming language for implementing server-side application logic is increasing in popularity, yet there is very little known about the architectural require...
Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko ...