Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
In this paper, we show that representation and reasoning techniques used in traditional knowledge engineering and the emerging Semantic Web can play an important role for heteroge...
Visual Language (VL) system development is getting increasingly sophisticated in part due to the arduous nature of user interface (UI) code development. This typically involves id...
Nita Goyal, Charles Hoch, Ravi Krishnamurthy, Bria...