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DAC
2005
ACM
14 years 11 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma
VLSID
2005
IEEE
89views VLSI» more  VLSID 2005»
14 years 11 months ago
Power Optimization in Current Mode Circuits
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
M. S. Bhat, H. S. Jamadagni
FCCM
2009
IEEE
165views VLSI» more  FCCM 2009»
14 years 5 months ago
Accelerating Quadrature Methods for Option Valuation
This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The arc...
Anson H. T. Tse, David B. Thomas, Wayne Luk
ISORC
2009
IEEE
14 years 5 months ago
Marte CCSL to Execute East-ADL Timing Requirements
In the automotive domain, several loosely-coupled Architecture Description Languages (ADLs) compete to proet of abstract modeling and analysis services on top of the implementatio...
Frédéric Mallet, Marie-Agnès ...
DSN
2008
IEEE
14 years 5 months ago
A characterization of instruction-level error derating and its implications for error detection
In this work, we characterize a significant source of software derating that we call instruction-level derating. Instruction-level derating encompasses the mechanisms by which co...
Jeffrey J. Cook, Craig B. Zilles