Power Optimization in Current Mode Circuits

We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in a current comparator circuit. Power reduction is achieved through turning off the redundant comparator circuits using a switch-architecture. Simulations are carriedout for current-mode flash ADC designs and literal generating circuits for MVL. We show that the simple switch architecture with minimum area overhead can be used to trade-off power dissipation with delay in these designs.

• Type: Conference
• Year: 2005
• Where: VLSID
• Authors: M. S. Bhat, H. S. Jamadagni
• Keywords: Computer Architecture, Current Comparator Circuit, Redundant Comparator Circuits, Trade-off Power Dissipation, VLSID 2005