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» A Logical Viewpoint on Architectures
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EFDBS
2003
15 years 7 months ago
Four-Level-Architecture for Closure in Interoperability
A definition of types in an information system is given from ld abstractions through data constructs, schema and definitions to physical data values. Category theory suggests tha...
B. Nick Rossiter, Michael A. Heather
187
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EDCC
2006
Springer
15 years 9 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 10 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
15 years 10 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
15 years 10 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus