12 search results - page 1 / 3 » A Low Overhead Fault Tolerant Coherence Protocol for CMP Arc... |
162
Voted
TPDS
2008
15 years 3 months ago
2008
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
157
Voted
HPCA
2007
IEEE
16 years 4 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
150
Voted
DAC
2011
ACM
14 years 3 months ago
2011
ACM
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
165
Voted
DSD
2008
IEEE
15 years 5 months ago
2008
IEEE
Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance is becoming increasingly important in computing systems. Shared memory i...
137
Voted
SBCCI
2005
ACM
15 years 9 months ago
2005
ACM
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...