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ICCAD
2000
IEEE
102views Hardware» more  ICCAD 2000»
14 years 16 hour ago
Provably Good Global Buffering Using an Available Buffer Block Plan
To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and b...
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu,...
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
13 years 7 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
DAC
2000
ACM
14 years 8 months ago
Convex delay models for transistor sizing
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapat...
ESANN
2001
13 years 9 months ago
Input data reduction for the prediction of financial time series
Prediction of financial time series using artificial neural networks has been the subject of many publications, even if the predictability of financial series remains a subject of ...
Amaury Lendasse, John Aldo Lee, Eric de Bodt, Vinc...
CORR
2007
Springer
127views Education» more  CORR 2007»
13 years 7 months ago
Common Reusable Verification Environment for BCA and RTL Models
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...
Giuseppe Falconeri, Walid Naifer, Nizar Romdhane