1609 search results - page 319 / 322 » A Microeconomic Scheduler for Parallel Computers |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
CHI
2007
ACM
14 years 8 months ago
2007
ACM
We present an observational study that was conducted to guide the design and development of technologies to support information flow during nurses' shift change in a hospital...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...