14 search results - page 2 / 3 » A Multi-Band Burst-Mode Clock and Data Recovery Circuit |
IEICET
2006
13 years 7 months ago
2006
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— This paper presents a passive filter for the front end of a high speed serial link receiver to aid timing recovery. The filter provides simultaneous lowpass and highpass tran...
CCECE
2009
IEEE
14 years 9 days ago
2009
IEEE
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...
MICRO
2003
IEEE
14 years 26 days ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
TVLSI
2010
13 years 2 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...