982 search results - page 20 / 197 » A Multiprocessor Communication Architecture For High Speed N... |
ICCCN
2007
IEEE
14 years 1 months ago
2007
IEEE
— Packet buffers in a smart network interface card are managed in a way to reduce any packet losses from high-speed burst incoming data. Currently, two types of packet buffer man...
ICNP
2006
IEEE
14 years 1 months ago
2006
IEEE
— The phenomenal growth of the Internet in the last decade and society’s increasing dependence on it has brought along, a flood of security attacks on the networking and compu...
TVLSI
2010
13 years 2 months ago
2010
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
ASPLOS
1992
ACM
13 years 11 months ago
1992
ACM
Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a ...