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» A Network Memory Architecture Model and Performance Analysis
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DATE
2005
IEEE
116views Hardware» more  DATE 2005»
14 years 2 months ago
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations
In today’s embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the u...
Ilya Issenin, Nikil D. Dutt
CODES
1998
IEEE
14 years 1 months ago
Schedulability analysis of heterogeneous systems for performance message sequence chart
Telecommunication systems are often specified in the standardized languages SDL and MSc. These languages allow only the specification of pure functional aspects. To remedy this pr...
Frank Slomka, Jürgen Zant, Lennard Lambert
IJCSA
2007
100views more  IJCSA 2007»
13 years 9 months ago
Using Artificial Neural networks for the modelling of a distillation column
The main aim of this paper is to establish a reliable model both for the steady-state and unsteady-state regimes of a nonlinear process. The use of this model should reflect the t...
Yahya Chetouani
ISSS
2002
IEEE
130views Hardware» more  ISSS 2002»
14 years 2 months ago
System-Level Modeling of a Network Switch SoC
We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a desig...
Andrew S. Cassidy, Christopher P. Andrews, Donald ...
CF
2010
ACM
14 years 2 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...