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» A Network Memory Architecture Model and Performance Analysis
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DAC
2008
ACM
14 years 8 months ago
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array fo
: Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRA...
Jing Li, Charles Augustine, Sayeef S. Salahuddin, ...
EUROPAR
2001
Springer
14 years 4 days ago
Performance of High-Accuracy PDE Solvers on a Self-Optimizing NUMA Architecture
High-accuracy PDE solvers use multi-dimensional fast Fourier transforms. The FFTs exhibits a static and structured memory access pattern which results in a large amount of communic...
Sverker Holmgren, Dan Wallin
JSA
2006
113views more  JSA 2006»
13 years 7 months ago
A power-efficient TCAM architecture for network forwarding tables
Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable m...
Taskin Koçak, Faysal Basci
IJON
2008
156views more  IJON 2008»
13 years 7 months ago
Analysis of the dynamical behavior of a feedback auto-associative memory
The dynamical behavior and the stability properties of fixed points in a feedback auto-associative memory are investigated. The proposed structure encompasses a multi-layer percep...
Mahmood Amiri, Sohrab Saeb, Mohammad Javad Yazdanp...
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
14 years 2 months ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu