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» A Network Memory Architecture Model and Performance Analysis
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WICON
2008
13 years 10 months ago
Channel assignment with partially overlapping channels in wireless mesh networks
Many efforts have been devoted to maximizing the network throughput with limited channel resources in multi-radio multi-channel wireless mesh networks. It has been believed that t...
Yong Ding, Yi Huang, Guo-Kai Zeng, Li Xiao
STOC
2004
ACM
61views Algorithms» more  STOC 2004»
14 years 9 months ago
The zero-one principle for switching networks
Recently, approximation analysis has been extensively used to study algorithms for routing weighted packets in various network settings. Although different techniques were applied...
Yossi Azar, Yossi Richter
FPL
2003
Springer
95views Hardware» more  FPL 2003»
14 years 2 months ago
Reconfigurable Hardware SAT Solvers: A Survey of Systems
By adapting to computations that are not so well supported by general-purpose processors, reconfigurable systems achieve significant increases in performance. Such computational sy...
Iouliia Skliarova, António de Brito Ferrari
HPCA
2006
IEEE
14 years 9 months ago
The common case transactional behavior of multithreaded programs
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen...
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
14 years 9 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne