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» A Network Memory Architecture Model and Performance Analysis
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DATE
2008
IEEE
170views Hardware» more  DATE 2008»
14 years 2 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
DAC
2006
ACM
14 years 1 months ago
Modeling and analysis of circuit performance of ballistic CNFET
With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-ana...
Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Tho...
DAC
2010
ACM
13 years 9 months ago
Network on chip design and optimization using specialized influence models
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
Cristinel Ababei
NCA
2003
IEEE
14 years 1 months ago
Performance analysis for a DiffServ-enabled network: The case of Relative Service
A lot of research work has recently focused on the exploitation of the DiffServ framework towards building reliable networking services that provide deterministic quality guarante...
Christos Bouras, Afrodite Sevasti
CCECE
2009
IEEE
14 years 27 days ago
Performance analysis of best effort support in broadband IEEE 802.16 networks
This paper presents a performance analysis of best effort support over the MAC protocol proposed in the IEEE 802.16 standard. We focus on the uplink channel since it is the critic...
Victor Rangel, Javier Gomez, Javier Chapa, Miguel ...