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» A Network Memory Architecture Model and Performance Analysis
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FCCM
2004
IEEE
269views VLSI» more  FCCM 2004»
13 years 11 months ago
FPGA Based Network Intrusion Detection using Content Addressable Memories
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). Current software-based NIDS are too compute intensive and can not ...
Long Bu, John A. Chandy
TSMC
1998
62views more  TSMC 1998»
13 years 7 months ago
Performance based design of high-level language-directed computer architectures
— This paper is concerned with the analytical modeling of computer architectures to aid in the design of high-level language-directed computer architectures. High-level language-...
Rajendra S. Katti, Mark L. Manwaring
ICPP
2007
IEEE
14 years 2 months ago
Architectural Challenges in Memory-Intensive, Real-Time Image Forming
The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial quest...
Anders Ahlander, H. Hellsten, K. Lind, J. Lindgren...
FPL
2010
Springer
210views Hardware» more  FPL 2010»
13 years 5 months ago
A Compact Transactional Memory Multiprocessor System on FPGA
In this paper we present a rapid prototyping platform on a single Field Programmable Gate Array (FPGA) with support for software transactional memory. The system is composed only b...
Matteo Pusceddu, Simone Ceccolini, Gianluca Palerm...
BROADNETS
2007
IEEE
14 years 2 months ago
Modeling and performance analysis of an improved DCF-based mechanism under noisy channel
The ISM free-licence band is highly used by wireless technologies such IEEE 802.11, Bluetooth as well as private wireless schemes. This huge utilisation increases dramatically the ...
Adlen Ksentini, Marc Ibrahim