Sciweavers

3629 search results - page 71 / 726
» A Network Memory Architecture Model and Performance Analysis
Sort
View
TCSV
2008
225views more  TCSV 2008»
13 years 7 months ago
Analysis and Efficient Architecture Design for VC-1 Overlap Smoothing and In-Loop Deblocking Filter
Abstract--In contrast to the macroblock-based in-loop deblocking filters, the filters of VC-1 perform all horizontal edges (for in-loop filtering) or vertical edges (for overlap sm...
Yen-Lin Lee, T. Q. Nguyen
ISLPED
1995
ACM
116views Hardware» more  ISLPED 1995»
13 years 11 months ago
Activity-sensitive architectural power analysis for the control path
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing ...
Paul E. Landman, Jan M. Rabaey
DATE
2007
IEEE
223views Hardware» more  DATE 2007»
14 years 2 months ago
CARAT: a toolkit for design and performance analysis of component-based embedded systems
Solid frameworks and toolkits for design and analysis of embedded systems are of high importance, since they enable early reasoning about critical properties of a system. This pap...
Egor R. V. Bondarev, Michel R. V. Chaudron, Peter ...
ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
14 years 14 hour ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
14 years 2 days ago
Active Pages: A Computation Model for Intelligent Memory
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
Mark Oskin, Frederic T. Chong, Timothy Sherwood