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» A Network Memory Architecture Model and Performance Analysis
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IESS
2007
Springer
165views Hardware» more  IESS 2007»
14 years 2 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
14 years 1 months ago
Formal performance analysis and simulation of UML/SysML models for ESL design
UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative perfo...
Alexander Viehl, Timo Schönwald, Oliver Bring...
EMSOFT
2009
Springer
14 years 14 days ago
Serving embedded content via web applications: model, design and experimentation
Embedded systems such as smart cards or sensors are now widespread, but are often closed systems, only accessed via dedicated terminals. A new trend consists in embedding Web serv...
Simon Duquennoy, Gilles Grimaud, Jean-Jacques Vand...
DAC
2000
ACM
14 years 6 days ago
Fast power grid simulation
The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance lim...
Sani R. Nassif, Joseph N. Kozhaya
ICPP
2009
IEEE
14 years 2 months ago
Perfomance Models for Blocked Sparse Matrix-Vector Multiplication Kernels
—Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architec...
Vasileios Karakasis, Georgios I. Goumas, Nectarios...