83 search results - page 7 / 17 » A New Combinational Logic Minimization Technique with Applic... |
ENTCS
2007
13 years 7 months ago
2007
Computing with failures is a typical programming technique in functional logic programs. However, there are also situations where a program should not fail (e.g., in a determinist...
ICCD
1996
IEEE
14 years 10 hour ago
1996
IEEE
For circuits where there may be latches with no reset line, we show how to replace some of them with combinational logic. All previous work in sequential optimization by latch rem...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
ITC
1995
IEEE
13 years 11 months ago
1995
IEEE
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
DATE
2000
IEEE
14 years 8 days ago
2000
IEEE
This paper presents a method for redundancy identification (RID) using multi-node logic implications. The algorithm discovers a large number of direct and indirect implications b...