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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 13 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ECOOPW
2000
Springer
13 years 11 months ago
Metadata and Adaptive Object-Models
Abstract. The unrelenting pace of change that confronts contemporary software developers compels them to make their applications more configurable, flexible, and adaptable. A way t...
Joseph W. Yoder, Reza Razavi
PREMI
2007
Springer
14 years 1 months ago
Discovery of Process Models from Data and Domain Knowledge: A Rough-Granular Approach
The rapid expansion of the Internet has resulted not only in the ever-growing amount of data stored therein, but also in the burgeoning complexity of the concepts and phenomena per...
Andrzej Skowron
BMCBI
2006
150views more  BMCBI 2006»
13 years 7 months ago
Cluster analysis of protein array results via similarity of Gene Ontology annotation
Background: With the advent of high-throughput proteomic experiments such as arrays of purified proteins comes the need to analyse sets of proteins as an ensemble, as opposed to t...
Cheryl Wolting, C. Jane McGlade, David Tritchler
DAC
2006
ACM
14 years 8 months ago
Novel full-chip gridless routing considering double-via insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...